Hardware implementation of radial-basis neural networks with Gaussian activation functions on FPGA

Abstract This article introduces a method for realizing the Gaussian activation function of radial-basis (RBF) neural networks with their hardware implementation on field-programmable gaits area (FPGAs). The results modeling FPGA chips different families have been presented. RBF various topologies synthesized and investigated. component implemented by this algorithm is an network four neurons latent layer one neuron sigmoid using 16-bit numbers fixed point, which took 1193 logic matrix gate (LUTs—LookUpTable). Each hidden designed as separate computing unit. speed total delay combination scheme block was 101.579 ns. functions occupies 106 LUTs, 29.33 absolute error ± 0.005. Spartan 3 family has used to get these results. Modeling other series also introduced in article. Hardware such allows them be real-time control systems high-speed objects.